1. Field of the Invention
The present invention is related to a semiconductor device and a manufacturing method thereof, especially to an alignment mark for superimposing a first electrode on an element active region with high accuracy in a semiconductor device having a trench-type element isolation structure.
2. Background of the Invention
In a manufacturing process of a semiconductor integrated circuit, an element isolation structure including an element isolation region needs to be formed in order to perfectly and separately control operation of each element without any electrical interference between the elements. What has been proposed as the method is a trench-type element isolation for forming a trench in a semiconductor substrate and embedding an insulating film therein.
Now, a conventional trench-type element isolation structure and its manufacturing method will be described in detail. FIG. 40 shows a sectional structure of a DRAM after the trench-type element isolation structure is formed. A silicon oxide film 2 (2A through 2C) is embedded in trenches formed in a semiconductor substrate 1. More specifically, an embedded silicon oxide film 2A is formed in an alignment mark region 11A, a relatively narrow embedded silicon oxide film 2B in a memory cell region 11B, and a relatively wide embedded silicon oxide film 2C in a peripheral circuit region 11C.
The surfaces of the silicon oxide film 2 in the trenches and the semiconductor substrate 1 are level, so that the whole surface of the semiconductor substrate 1 is flat.
FIGS. 41 through 47 are sectional views illustrating a manufacturing process of the DRAM shown in FIG. 40. Now, the manufacturing process will be described in detail, referring to those figures.
A silicon oxide film 3 and a silicon nitride film 4 are formed on the semiconductor substrate 1. Then, a predetermined area of those films are removed by photolithography and dry etching to form trenches 10 (10A through 10C) to a predetermined depth in the semiconductor substrate 1, as shown in FIG. 41. More specifically, a relatively wide trench 10A is formed in the alignment mark region 11A, a relatively narrow trench 10B in the memory cell region 11B, and a relatively wide trench 10C in the peripheral circuit region 11C.
After side and bottom faces of the trenches 10 are thermally oxidized as shown in FIG. 42, the silicon oxide film 2 is deposited by a LPCVD method. At this time, while film thickness on the wide trenches 10A and 10C is proportional to what is actually deposited thereon along the shape of those trenches, film thickness on the narrow trench 10B is thicker than what is actually deposited thereon because the trench 10B has been filled by the silicon oxide film 2 in the early deposition.
In order to reduce absolute difference in level, as shown in FIG. 43, a resist pattern 5 is formed only on the relatively wide embedded silicon oxide film 2 by photolithography, and the silicon oxide film 2 is partly removed by dry etching.
After the resist pattern 5 is removed, the whole surface of the semiconductor substrate 1 is polished by a CMP (Chemical Mechanical Polishing) method to remove the silicon oxide film 2 formed on the silicon nitrogen film 4 and a part of the silicon oxide film 2 filled in the trenches 10A through 10C as shown in FIG. 44.
The silicon nitrogen film 4 and the silicon oxide film 3 are, as shown in FIG. 45, removed by using phosphoric acid and hydrofluoric acid, respectively, to form the embedded silicon oxide film 2A in the alignment mark region 11A, the embedded silicon oxide film 2B in the memory cell region 11B, and the embedded silicon oxide film 2C in the peripheral circuit region 11C, completing the trench-type element isolation structure.
Then, a gate oxide film 6 is formed by thermal oxidation, and a polysilicon film 7 doped with phosphorus and a tungsten silicide film 8 are deposited thereon, as shown in FIG. 46.
The embedded silicon oxide film 2A (alignment mark) formed in the alignment mark region 11A in the element isolation forming process is used in photolithography to form a pattern for superimposing a gate electrode on the element isolation region. Then, as shown in FIG. 47, a gate electrode 14 is formed in the memory cell region 11B and the peripheral circuit region 11C by partly removing the tungsten silicide film 8 and the polysilicon film 7 by dry etching.
The above-described conventional semiconductor device (DRAM) and its manufacturing method have some problems discussed below.
In patterning, the gate electrode 14 which is a first electrode material needs to be superimposed on an active region so that a pattern is formed in a predetermined area of the active region. For this, the alignment mark 2A formed in the alignment mark region 11A in the element isolation forming process is used.
Typical alignment methods includes a first method for recognizing a mark by detecting diffracted light with no photosensitivity to resists, and a second method for detecting a mark by recognizing picture information. The first method requires a difference in level produced by irregularity of the mark formed in the semiconductor substrate. In the second method, it is required either to detect fundamental mark information by transmitting light through the gate electrode material or to recognize mark information in accordance with a difference in level.
However, there is no difference in level in an alignment mark portion of the conventional semiconductor device with the trench-type element isolation structure, so that it is difficult to apply the first method which requires a difference in level to detect a mark. Further, as the silicide film which is a part of the gate electrode material does not transmit light, detection by the second method is also difficult.
Consequently, a S/N ratio of a mark detection signal falls and accuracy in alignment is reduced, thereby failing to superimpose a gate electrode in its formation.
Further, accuracy in alignment can be increased by forming the embedded silicon oxide film 2A in the trench lower than the surface of the semiconductor substrate, by which, however, the embedded silicon oxide films 2B and 2C simultaneously formed in the element forming region (memory cell region 11B and peripheral circuit region 11C) are also lowered.
This causes electric field concentration from the gate electrode, and hump in current/voltage characteristics of a transistor, increasing variation in threshold voltage and current in stand-by condition.
At the same time, as deposited thick in edges of the embedded silicon oxide films 2B and 2C, the gate electrode material remains in the edges in electrode etching, resulting in reduction in yield of elements.
When the embedded silicon oxide film 2A in the trench is formed higher than the surface of the semiconductor substrate, accuracy in alignment is increased, and hump in current/voltage characteristics of a transistor less occurs. This, however, increases difference in level in edges of the trenches and increases film thickness of the gate electrode material in upper portions of the edges. As the result, the gate electrode material remains in the edges in electrode etching, reducing yield of elements.